1. Field of the Invention
The present invention generally relates to charge pump circuits, for example, for use in a phase locked loop (PLL) system.
2. Description of the Prior Art
FIG. 1 illustrates a conventional PLL utilizing a digital phase comparison circuit 4. A reference oscillation signal is produced by a reference oscillation signal generating circuit 1 and is provided to a frequency-dividing circuit 2, in which it is frequency-divided to provide a frequency-divided signal R at an output terminal of the circuit 2. The frequency-divided signal R has a reference frequency, for example, of 25 kHz. The output terminal of the frequency-dividing circuit 2 is coupled with an input terminal R' of the digital phase comparison circuit 4 to provide the frequency-divided signal R thereto as a first phase comparison signal.
A voltage controlled oscillator (VCO) 7 produces an oscillation signal which it supplies to the input of a variable frequency-dividing circuit 3 simultaneously with the provision of the reference oscillation signal to the frequency-dividing circuit 2. The variable frequency-dividing circuit 3 divides the frequency of the oscillation signal from the VCO 7 by a divisor N to provide a frequency-divided signal V which it supplies to a second input terminal V' of the digital phase comparison circuit 4 as a second phase comparison signal.
With reference to FIG. 2, the digital phase comparison circuit 4 includes nine NAND gates connected as shown therein. With reference also to FIG. 3, the digital phase comparison circuit 4 is operative to provide a first phase difference signal U at a first output terminal U' thereof and a second phase comparison signal D at a second output terminal D' thereof in response to a phase difference between the first and second phase comparison signals R and V received at the input terminals R' and V', respectively. More specifically, when the first phase comparison signal V is delayed in phase with respect to the second phase comparison signal R, as shown in the left side of FIG. 3, the first phase difference signal U changes from a logic "1" state (a high voltage level) to a logic "0" state (a low voltage level) upon a transition of the phase comparison signal R from a logic "1" state to a logic "0" state. The first phase difference signal U thereafter remains in the logic "0" state until the phase comparison signal V subsequently falls from a logic "1" state to a logic "0" state, whereupon the first phase difference signal U rises to a logic "1" state. The second phase difference signal D remains in a logic "1" state so long as the phase of the first phase comparison signal R leads that of the second phase comparison signal V.
However, at such times that the phase of the second phase comparison signal V leads that of the first phase comparison signal R, as shown in the right hand side of FIG. 3, the first phase difference signal U remains in a logic "1" state, while the second phase difference signal D changes from a logic "1" state to a logic "0" state when the second phase comparison signal V falls from a logic "1" state to a logic "0" state and thereafter remains in a logic "0" state until the first comparison signal R also falls from a logic "1" state to a logic "0" state, whereupon the second phase difference signal D is raised to a logic "1" state.
With reference again to FIG. 1, the first and second phase difference signals U and D are supplied to respective inputs of a charge pump circuit 5. With reference also to FIG. 4, it will be seen that the charge pump circuit 5 includes a p-channel field effect transistor (FET) Qa whose gate is connected to output U' of the digital phase comparison circuit 4 to receive the first phase difference signal U therefrom and whose drain-source circuit is coupled between a source of positive power voltage +V.sub.DD and an output terminal 20 of the charge pump circuit 5. The charge pump circuit 5 also includes an n-channel FET Qb whose gate electrode is coupled through an inverter Qc with output D of the digital phase comparison circuit 4 to receive the second phase difference signal D therefrom. The source-drain path of the FET Qb is coupled between the output terminal 20 of the charge pump circuit 5 and a circuit ground.
A loop filter 6 includes an operational amplifier Qd having an inverting input terminal coupled through an input resistor Ra with the output terminal 20 of the charge pump circuit 5. An output terminal of the operational amplifier Qd is coupled with a control voltage terminal of the VCO 7. A first feedback capacitor Ca is coupled between the output terminal of the operational amplifier Qd and its inverting input terminal. A second feedback capacitor Cb has a first terminal connected with the output terminal of the operational amplifier Qd and a second terminal connected with a first terminal of a feedback resistor Rb having a second terminal connected with the inverting input terminal of the operational amplifier Qd. In this manner, the loop filter 6 takes the form of a mirror integrating circuit.
At such times that the phase of the first phase comparison signal R leads the phase of the second phase comparison V, the voltage applied to the gate of the FET Qa is periodically brought low by the first phase difference signal U to turn ON the FET Qa. Since the second phase difference signal D remains at a logic "1" state (high voltage) the gate of the FET Qb remains essentially at ground potential, so that the FET Qb is OFF. Accordingly, while the phase of the first phase comparison signal R leads that of the second phase comparison signal V, the loop filter 6 is charged by the power source voltage +V.sub.DD whenever the first phase difference signal U goes low in a logic "0" state. Conversely, at such times that the phase of the second phase comparison signal V leads that of the first phase comparison signal R, the FET Qa is maintained in an OFF state by the high voltage level of the first phase difference signal U in the logic "1" state, while the FET Qb is turned ON periodically by the high voltage level at the output of the inverter Qc produced at such times that the second phase difference signal D is in a logic "0" state so that the loop filter 6 is then discharged through the FET Qb. However, when both of the first and second phase difference signals U and D are in a logic "1" state, FETs Qa and Qb are both turned OFF so that the loop filter 6 is neither charged nor discharged. Accordingly, the loop filter 6 produces a dc voltage level at the output terminal thereof corresponding with the phase difference between the first and second phase difference signals U and D.
As noted above, the dc voltage level produced at the output of the loop filter 6 is applied to the control voltage terminal of the VCO 7 so that, in a stationary state, the VCO 7 produces an oscillation signal whose frequency is N times the frequency of the phase comparison signal R. The frequency dividing circuit 2, the variable frequency-dividing circuit 3, the digital phase comparison circuit 4 and the charge pump circuit 5 may be fabricated as a single chip integrated circuit 15 (see "Practical Use Guide to PLL", pages 125-127, dated Aug. 30, 1974, by Seibundoshinkosha and Japanese Laid-Open Pat. No. 51-139758 published Dec. 2, 1976).
With reference again to FIG. 2, the phase comparison circuit 4 ideally provides the first and second phase difference signals U and D in a logic "1" state whenever the phase comparison signals R and V are in phase. However, due to the inherent propagation delays of the circuit elements comprising the phase comparison circuit 4, upon the simultaneous high to low logic state transitions of the in-phase first and second phase comparison signals R and V (as shown by the solid line waveforms in FIG. 5A) both the first and second phase difference signals U and D are then brought to a logic "0" state for a brief but significant period of time. When the second phase comparison signal V becomes delayed in phase with respect to the first phase comparison signal R by a very small amount as shown by the dashed line in FIG. 5A, the first and second phase difference signals U and D are suddenly placed in logic states similar to those illustrated in the left-hand side of FIG. 3, although a brief interval may exist during which both signals are simultaneously in a logic "0" state. Alternatively, where the second phase comparison signal V becomes advanced in phase by a very small amount with respect to the first phase comparison signal R the first and second phase difference signals U and D are suddenly placed in states similar to those illustrated in the right-hand side of FIG. 3. The resulting relationship between the phase difference .DELTA..THETA., (that is, the phase difference of the second phase comparison signal V with respect to the first phase comparison signal R) and the charging and discharging periods controlled by the first and second phase difference signals U and D, is illustrated by the line A in FIG. 6. In FIG. 6, the axis of ordinates represents the relative charging and discharging periods of the loop filter 6, while the axis of abscissas represents the relative phase delay or advance of the second phase comparison signal V with respect to the first phase comparison signal R. It will be seen from FIG. 6 that an indefinite charging period exists where the signals R and V are either in phase or only slightly out of phase so that the operation of the PLL is unstable under such conditions.
In order to overcome the foregoing problem, it has been proposed that a dead zone interval be introduced for phase differences .DELTA..THETA. which do not exceed a predetermined magnitude, so that, when the first and second phase comparison signals R and V are in phase, the first and second phase difference signals U and D are reliably maintained in a logic "1" state. Accordingly, the combination of the operational delay times of the NAND gates and other circuit elements forming the phase comparison circuit 4 are changed so that the relationship of the charging and discharging periods to the phase difference .DELTA..THETA. is instead expressed by the broken line B of FIG. 6. That is, even when the second phase comparison signal V is phase delayed with respect to the first phase comparison signal R by a relatively small amount (for example, as shown by the solid line waveform illustrated in FIG. 5B) or when the second phase comparison signal V is advanced in phase with respect to the first phase comparison signal R (for example, as shown by the dashed line waveform in FIG. 5B), the first and second phase difference signals U and D are maintained in a logic "1" state. Accordingly, unless the phase difference .DELTA..THETA. exceeds a minimum predetermined magnitude defining the extremes of the dead zone interval, the charge pump circuit 5 will neither charge nor discharge the loop filter 6.
Where the phase comparison circuit 4 and the charge pump circuit 5 are constructed as above so that an indefinite charging period exists (as represented by the discontinuous line A in FIG. 6) or where a dead zone interval is provided (as shown by the broken line B of FIG. 6), the phase locked loop exhibits a different natural frequency .omega.n and damping coefficient .xi. when operating in a phase locked condition than while operating in an unlocked condition. Accordingly, the natural frequency and damping coefficient of the phase-locked loop cannot be optimized and, consequently, the purity of the oscillation frequency of the VCO 7 deteriorates. The foregoing results in the deterioration of the carrier-to-noise ratio where, for example, the output of the VCO 7 is utilized to provide a local oscillation signal for a radio receiver. Moreover, where the conventional phase locked loop as described above, is utilized for FM modulation, the modulated output signal exhibits distortion as a consequence of deterioration in the purity of the oscillation frequency.
A further disadvantage inherent in the conventional phase locked loop described above is an unavoidable dependency between the loop gain and the cut-off frequency of the loop filter 6. That is, although the loop gain can be adjusted by selecting the ratio between the resistance values of the resistors Ra and Rb, this likewise changes the cut-off frequency of the loop filter 6. The design of the conventional phase locked loop, therefore, is inherently inflexible. In addition, the conventional phase locked loop requires the use of the operational amplifier Qd for constructing the loop filter 6, resulting in a poor space factor and increased cost.